Category: Processors
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TIER IV is opening its autonomous-driving AI chip designs publicly. The JST-backed programme combines dedicated Transformer acceleration, open compiler tooling, and formal verification for edge systems.
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LX Semicon has begun mass production of its automotive MCU. The 40MHz Cortex-M3 device will enter Hyundai and Kia vehicles after around three years of development, qualification, and supply-chain preparation.
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Researchers have demonstrated a 28nm SRAM compute-in-memory macro for edge-AI. The design targets signed arithmetic, routing congestion, and switching overhead while supporting INT8 and BF16 computation.
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D-Wave has demonstrated an error-detecting gate for scalable quantum architectures. The operation achieved approximately 99.9% fidelity while retaining dual-rail error detection.
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AMD’s embedded revenue climbed nineteen per cent during the quarter. New processors, adaptive systems-on-chip, and modules broaden its industrial and edge-computing portfolio.
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Ambiq has released open-source profiling software for Apollo edge-AI hardware. The alpha tool measures execution cycles, memory use, and optional real-time power.
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NEO has combined two memory concepts for future AI processors. X-SRAM targets denser on-chip storage while 3D X-DRAM addresses external memory capacity.
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Actions and Ceva have integrated Bluetooth HDT into audio silicon. ATS296X devices target lossless multichannel sound, lower latency, and faster wireless updates.
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Alif has licensed Keil MDK for its embedded AI families. The agreement adds Arm-native development, debug, middleware, and simulation support across Ensemble and Balletto devices.
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Researchers moved one spin qubit across four isolated silicon registers. The five-qubit processor completed weight-four parity checks required by surface-code error correction.