Category: Design engineering
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Variscite has launched its first SMARC module family today, globally. The VAR-SMARC-MX8M-PLUS targets compact industrial and medical edge designs, combining NXP’s i.MX 8M Plus with dual Gigabit Ethernet (IEEE1588 support), expanded USB, and an on-module TPM 2.0 security device.
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Component obsolescence remains a persistent risk for electronics manufacturers globally. ByteSnap Design has launched a free interactive BOM Health Self-Assessment tool to help engineering leaders quantify their exposure and evaluate whether existing BOM management processes are sufficient before disruption occurs.
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Cree LED is targeting brighter displays using less power now. Its OptiLamp components integrate driver and control intelligence inside each LED pixel, aiming to cut system complexity while improving image quality and long-term maintainability in large-format display deployments.
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The Switch has added a battery-interface current limiter for DC. Its Electronic Current Limiter clamps fault current in microseconds, helping hybrid and electric vessels keep DC-link voltage stable during battery-side faults.
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Munich researchers have built Europe’s first 7nm AI chip prototype. The RISC-V, neuromorphic design targets ultra-low-power on-device inference, with an eye on security-sensitive industrial and medical workloads. TUM’s MACHT-AI centre is backing further tape-outs on advanced FinFET nodes.
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The FDA’s QMSR is now effective for US device makers. The rule updates 21 CFR Part 820 by incorporating ISO 13485:2016 by reference, shifting both documentation expectations and inspection mechanics for medical electronics manufacturers selling into the US market.
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Microchip has broadened its Cortex-M0+ microcontroller range again today, globally. The new PIC32CM PL10 family targets 5 V, noise-tolerant embedded control, with pin compatibility intended to ease migration from AVR Dx designs in industrial, appliance, and automotive subsystems.
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January’s electronics agenda narrowed around power, packaging, and policy constraints. CES announcements pushed compute into rack-scale platforms, while memory supply and advanced packaging capacity dictated what could realistically ship. Export controls and EU security obligations tightened the design perimeter around compliance, updateability, and regional configuration management.
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CSA Catapult is pushing vertical GaN as net-zero infrastructure enabler. A new white paper argues GaN-on-GaN vertical devices can handle higher voltages and power densities than lateral structures, with implications for EV charging, renewable grids, and data centre power conversion.
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Microsoft has detailed Maia 200, its latest inference accelerator silicon. Built on TSMC 3nm, the chip pairs FP8/FP4 tensor cores with 216GB HBM3e, targeting higher token-throughput per watt in Azure-scale deployments.