Category: Design engineering
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XPENG is advancing VLA 2.0 and updating European vehicles now. Global delivery of the next-generation vision-to-action driving stack is planned from 2027, while XOS 5.8.7 begins rolling out in Europe this month with refinements to ACC, lane centring, and connectivity.
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Delta has acquired its German building automation integration partner outright. The deal folds Delta Controls Germany’s European integrator network into Delta’s smart-building portfolio, as building automation and control requirements tighten across the region.
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Molex pushed coaxial test assemblies to 145 GHz limits now. Its latest Cardinal multi-port coaxial assemblies target dense lab setups for AI interconnect and 5G/6G validation, with phase-matched connections and data characterisation rates up to 448 Gbps.
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L3Harris says additive manufacturing is reshaping airbreathing hypersonic propulsion production. The company reports a tenfold reduction in 3D-printed component lead times under a US DoD manufacturing programme.
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Iridium has unveiled a three-radio module for global IoT deployments. The Iridium 9604 integrates Iridium SBD satellite, LTE-M cellular, and multi-constellation GNSS, with commercial availability set for June 2026.
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SEALSQ increased its EeroQ stake to back helium-qubit development further. The follow-on investment targets a US-centred quantum hardware roadmap, and a planned Geneva demonstration linking quantum processors with post-quantum secure semiconductor components.
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Rice researchers patterned diamond cooling layers across 2-inch semiconductor wafers. The team reports selective-area diamond growth that cut device operating temperatures by 23°C, using process flows intended to fit heterogeneous integration and high-power electronics.
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Tower and Xanadu have tightened their silicon photonics partnership further. The companies have co-engineered a production flow for Xanadu’s custom material stack on Tower’s high-volume SiPho platform, targeting manufacturable photonic quantum hardware for fault-tolerant systems.
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MIT has demonstrated paired PUFs using standard CMOS fabrication steps. A new “twin fingerprint” method lets two chips authenticate each other directly, avoiding external storage of secret fingerprint data, and targeting power-constrained paired devices such as medical sensors.
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Nordson will showcase coating and soldering systems at APEX 2026. In Anaheim, the company plans live demonstrations focused on process control, traceability, and higher-yield PCB assembly, including updates to its ASYMTEK Select Coat platform and its SELECT Synchro selective soldering line.