Category: Design engineering
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SK hynix and Sandisk have published initial HBF interface specifications. Capacities reach 512GB while three bandwidth grades span approximately 0.4TB/s to 3.0TB/s.
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Researchers moved one spin qubit across four isolated silicon registers. The five-qubit processor completed weight-four parity checks required by surface-code error correction.
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ROHM has quadrupled terahertz output without enlarging its semiconductor die. The RTD-EVK-G2 kit targets lower-cost evaluation for sensing, imaging, and non-destructive inspection.
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Palomino has completed its acquisition of interconnect specialist Vega Links. The combined organisation is developing copper, MicroVCSEL, and MicroLED chipsets for connections spanning short-reach artificial-intelligence computing infrastructure.
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China has substantially strengthened protections for integrated-circuit layout designs nationwide. Revised rules raise originality requirements, clarify commercial use, and introduce stronger infringement remedies from 15 October.
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Arm has added runtime evidence to AI-assisted software performance analysis. Dynamic Insights links supported profiling runs with LLM reasoning while keeping the underlying measurements available for engineers to inspect.
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Bruker has launched two detectors for faster nanoscale materials analysis. The systems combine direct-electron, X-ray, and back-scattered-electron measurements for semiconductor, thin-film, battery, and nanostructure workflows.
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CEA-Leti is moving three dimensional integration into future AI architectures. Fine pitch hybrid bonding is being developed alongside new approaches to power, memory, cooling, and test.
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Delta’s automotive charging process has reached ASPICE Capability Level 2. The assessment covers managed development across engineering, testing, and final validation.
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Altus is expanding its Redditch headquarters around connected production lines. The centre will integrate SMT, through hole, backend, and component management equipment.