Category: Design engineering
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Anritsu has introduced Tensor, an AI-assisted vector network analyser platform. The source-per-port architecture supports RF, microwave, millimetre-wave, and sub-THz characterisation.
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Adhesive selection demands equal attention to material performance and process. Peter Swanson, Executive Chair and Founder at Intertronics, explains why production trials, surface preparation, dispensing, curing, and QA must shape adhesive specification.
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Our latest issue examines resilient electronics supply chains under pressure. It spans medical technology, AI-ready networks, component availability, data integrity, and connected-device compliance.
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Imec has advanced its 300mm RF silicon interposer platform further. The work adds embedded capacitors, passive modelling, and laser-assisted bonding for III-V chiplets on Si-CMOS.
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Siemens and Samsung Foundry are extending advanced-node EDA collaboration flows. The work covers verification, test, packaging, analogue, RF, and implementation.
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RISC-V Summit Europe has opened in Bologna around deployable hardware. The programme spans embedded systems, AI, automotive, security, software, and space.
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CEA-Leti and GlobalFoundries are extending FD-SOI research through Europe’s FAMES. The pilot line targets low-power, sovereign silicon for advanced applications.
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Keysight will manage Leonardo UK test equipment for five years. The agreement covers calibration, repair, digital asset management, and lifecycle support across UK sites.
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CGD and NXP are collaborating on GaN power-conversion system designs. The work targets data-centre, automotive, and industrial designs needing higher efficiency and density.
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CSA Catapult will become the UK’s Semiconductor Catapult this summer. The transition broadens support for chip R&D, validation, commercialisation, and AI hardware deployment.