NEO has combined two memory concepts for future AI processors. X-SRAM targets denser on-chip storage while 3D X-DRAM addresses external memory capacity.
Microchip and Micron linked PCIe 6 switching with production SSDs. The FMS demonstration targets scalable storage for AI, cloud, and high-performance computing systems.
SK hynix and Sandisk have published initial HBF interface specifications. Capacities reach 512GB while three bandwidth grades span approximately 0.4TB/s to 3.0TB/s.
Renesas restarted phased wafer production at Kawashiri one day early. Pre-earthquake input capacity is targeted within approximately three weeks.
Researchers moved one spin qubit across four isolated silicon registers. The five-qubit processor completed weight-four parity checks required by surface-code error correction.
ROHM has quadrupled terahertz output without enlarging its semiconductor die. The RTD-EVK-G2 kit targets lower-cost evaluation for sensing, imaging, and non-destructive inspection.