Category: News
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Arm is joining EuroCDP as its first commercial IP provider. European start-ups, SMEs and researchers will gain access to processor IP, tools, training and design support from architecture exploration through tape-out.
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ams OSRAM has demonstrated 32Gbps thin-film VCSEL arrays for AI. The 850nm platform uses addressable 25µm-pitch emitters, silicon TSV integration and a highly parallel architecture designed to reduce optical interconnect energy.
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SEALSQ plans a Swiss centre for post-quantum semiconductor personalisation capabilities. The CHF40–60 million Jura proposal covers secure provisioning, testing, certification and potential ASIC design, with more than 250 direct jobs targeted by year eight.
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imec has demonstrated a 400Gbps optical link using low-voltage APDs. The 300mm silicon photonics device combines 100GHz bandwidth, 5V operation and internal gain while improving receiver sensitivity by 3dB.
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Kelington will support critical infrastructure at Tata’s Dholera semiconductor fab. The collaboration targets tool hook-up, production readiness, and local engineering capability for the planned 300mm facility.
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Omron has launched distributed safety I/O with local machine logic. NXR-S combines 15ms response capability, CIP Safety management, IP67 construction, and browser-based diagnostics for decentralised machinery architectures.
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L&T and Tata are linking chip design with manufacturing capabilities. The partnership will examine fabrication, packaging, and design-for-manufacturing optimisation for current and future semiconductor products.
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SCL has launched an indigenous execution system for fab automation. DMIS covers semiconductor production from order booking and wafer fabrication through final packaging and shop-floor control.
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AI packaging is moving beyond established CoWoS-S interposer limits now. TrendForce expects CoWoS-L to remain the mainstream approach through 2028 as accelerator packages add compute dies and HBM.
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Dnotitia has received first silicon for its dedicated vector processor. Chip-level characterisation is under way before planned ASIC system evaluations during the fourth quarter.