Category: Electronics
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Teradyne has launched Iris 100 for production microLED optical testing. The platform measures individual emitters across large arrays and combines optical characterisation with UltraFLEXplus electrical test infrastructure.
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ITRI has unveiled a 3.2Tbps silicon-photonics engine for AI networks. The design doubles its previous 1.6T generation while more than 20 partners develop supporting design, fabrication, test and packaging capability.
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Lumentum has developed an eight-wavelength laser source for AI optics. The pluggable DWDM module delivers up to 24dBm per wavelength while targeting serviceable external illumination for co-packaged and near-packaged optical systems.
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Molex has introduced VersaBeam Mini for denser AI optical links. The 16-fibre expanded-beam connector fits a 3.5 x 9mm footprint, supports up to 3,456 fibres per 1RU and enters limited sampling in Q4 2026.
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ams OSRAM has demonstrated 32Gbps thin-film VCSEL arrays for AI. The 850nm platform uses addressable 25µm-pitch emitters, silicon TSV integration and a highly parallel architecture designed to reduce optical interconnect energy.
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SEALSQ plans a Swiss centre for post-quantum semiconductor personalisation capabilities. The CHF40–60 million Jura proposal covers secure provisioning, testing, certification and potential ASIC design, with more than 250 direct jobs targeted by year eight.
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imec has demonstrated a 400Gbps optical link using low-voltage APDs. The 300mm silicon photonics device combines 100GHz bandwidth, 5V operation and internal gain while improving receiver sensitivity by 3dB.
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SCL has launched an indigenous execution system for fab automation. DMIS covers semiconductor production from order booking and wafer fabrication through final packaging and shop-floor control.
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AI packaging is moving beyond established CoWoS-S interposer limits now. TrendForce expects CoWoS-L to remain the mainstream approach through 2028 as accelerator packages add compute dies and HBM.
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Dnotitia has received first silicon for its dedicated vector processor. Chip-level characterisation is under way before planned ASIC system evaluations during the fourth quarter.