Category: Design engineering
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IBM is designing a processor supporting native Arm and Z. The 2 nm chip contains 11 cores above 5.7 GHz while executing both instruction architectures within each core.
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Achronix has released JESD204C IP for high-bandwidth Speedster7t FPGA systems. The core supports 32 Gbps lanes, deterministic latency, and aggregate serial throughput reaching 1 Tbps.
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Celera has raised $30 million for analogue design automation expansion. The Series B will support product development, customer programmes, and engineering growth in California and Portugal.
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Nagoya researchers cut contact resistance in thin p-type gallium nitride. An ultrathin magnesium layer and short anneal preserve surface quality while improving current injection.
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Kyoto researchers have demonstrated silicon-carbide transistors operating reliably above 600°C. Bottom-gate and double-well structures improve threshold control and suppress high-temperature leakage in extreme-environment electronics.
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Arduino has opened pre-orders for its industrial VENTUNO Q platform. The board combines Qualcomm edge-AI processing with deterministic STM32 control for robotics and sensor-rich embedded systems.
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Perceptia has released pPLL03 design IP for Samsung 14LPU silicon. The block supports 4GHz operation, fractional-N synthesis, low jitter, and compact SoC integration.
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SiFive has launched rackable RISC-V hardware for datacentre development workloads. BigSky combines 32 P870-D cores with DDR5, PCIe 5.0, Linux, and GPU support.
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Quintessent has begun sampling its quantum-dot DWDM comb laser platform. The eight-wavelength source targets simpler optical interconnects for expanding AI clusters.
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Intel has detailed three architectures spanning datacentre, inference, and edge. Diamond Rapids, Crescent Island, and Wildcat Lake combine new compute, memory, packaging, and interconnect technologies.